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XC18V00 Series In-System-Programmable Configuration PROMs
Product Specification
DS026 (v5.2) January 11, 2008
0
Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs

* *
Low-Power Advanced CMOS FLASH Process Dual Configuration Modes

Endurance of 20,000 Program/Erase Cycles Program/Erase Over Full Industrial Voltage and Temperature Range (-40C to +85C) * * * * *
Serial Slow/Fast Configuration (up to 33 MHz) Parallel (up to 264 Mb/s at 33 MHz)
* * * *
IEEE Std 1149.1 Boundary-Scan (JTAG) Support JTAG Command Initiation of Standard FPGA Configuration Simple Interface to the FPGA Cascadable for Storing Longer or Multiple Bitstreams
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals 3.3V or 2.5V Output Capability Design Support Using the Xilinx ISETM FoundationTM Software Packages Available in PC20, SO20, PC44, and VQ44 Packages Lead-Free (Pb-Free) Packaging
Description
Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
X-Ref Target - Figure 1
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After CE and OE are enabled, data is available on the PROM's DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes. Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.
OE/RESET
CLK
CE
TCK TMS TDI TDO
Control and JTAG Interface
Data
CEO
Memory
Address
Data
Serial or Parallel Interface
D0 DATA Serial or Parallel Mode
7
D[1:7] Parallel Interface
CF
DS026_01_040204
Figure 1: XC18V00 Series Block Diagram
(c) 1999-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
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XC18V00 Series In-System-Programmable Configuration PROMs
Pinout and Pin Description
Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC packages. Table 1: Pin Names and Descriptions
Pin Name
D0
BoundaryScan Order
4 3
Function
DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA IN
Pin Description
D0 is the DATA output pin to provide data for configuring an FPGA in serial mode.
44-pin VQFP
40
44-pin PLCC
2
20-pin SOIC & PLCC
1
D1
6 5
D2
2 1
D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Slave Parallel/SelectMAP mode. D1-D7 remain in high-Z state when the PROM operates in serial mode. D1-D7 can be left unconnected when the PROM is used in serial mode.
29
35
16
42
4
2
D3
8 7
27
33
15
D4
24 23
9
15
7(1)
D5
10 9
25
31
14
D6
17 16
14
20
9
D7
14 13
19
25
12
CLK
0
Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. When Low, this input holds the address counter reset and the DATA output is in a highZ state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. When CE is High, the device is put into lowpower standby mode, the address counter is reset, and the DATA pins are put in a high-Z state. Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command.
43
5
3
OE/ RESET
20 19 18
DATA IN DATA OUT OUTPUT ENABLE DATA IN
13
19
8
CE
15
15
21
10
CF
22 21
DATA OUT OUTPUT ENABLE
10
16
7(1)
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XC18V00 Series In-System-Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (Cont'd)
Pin Name
CEO
BoundaryScan Order
12 11
Function
DATA OUT OUTPUT ENABLE
Pin Description
Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. GND is the ground connection.
44-pin VQFP
21
44-pin PLCC
27
20-pin SOIC & PLCC
13
GND TMS MODE SELECT
6, 18, 28 & 41 5
3, 12, 24 & 34 11
11 5
The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50 k resistive pull-up to provide a logic 1 to the device if the pin is not driven. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50 k resistive pull-up to provide a logic 1 to the device if the pin is not driven. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50 k resistive pull-up to provide a logic 1 to the system if the pin is not driven. Positive 3.3V supply voltage for internal logic. Positive 3.3V or 2.5V supply voltage connected to the input buffers(2) and output voltage drivers. No connects.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
VCCINT VCCO
17, 35 & 38(3)
23, 41 & 44(3)
18 & 20(3) 19
8, 16, 26 & 36 14, 22, 32 & 42 1, 2, 4, 11, 12, 20, 22, 23, 24, 30, 32, 33, 34, 37, 39, 44 1, 6, 7, 8, 10, 17, 18, 26, 28, 29, 30, 36, 38, 39, 40, 43
NC
Notes:
1. 2. 3. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF D4 programming option can be set to override the default and route the CF function to pin 7 in the Serial mode. For devices with IDCODES 0502x093h, the input buffers are supplied by VCCINT. For devices with IDCODES 0503x093h, the following VCCINT pins are no-connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC package, and pin 20 in 20-pin SOIC and 20-pin PLCC packages.
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XC18V00 Series In-System-Programmable Configuration PROMs
Pinout Diagrams
DATA(D0) D2 CLK TDI TMS TCK CF/D4* 1 2 3 4 5 6 7 8 9 10 20 19 18 VCCINT* VCCO VCCINT* TDO D1 D3 D5 CEO D7 GND
NC CLK D2 GND D0 NC VCCINT* NC VCCO VCCINT* NC
VCCINT*
18 19 20 21 22 23 24 25 26 27 28
3
2
1
20
NC OE/RESET D6 CE VCCO VCCINT* GND D7 NC CEO NC
TDI TMS TCK D4/CF* OE/RESET
DS026_12_20051007
4 5 6 7 8 9
19 18
VCCO
CLK
D2
D0
NC NC TDI NC TMS GND TCK VCCO D4 CF NC
7 8 9 10 11 12 13 14 15 16 17
PC44/PCG44 Top View
39 38 37 36 35 34 33 32 31 30 29
NC NC TDO NC D1 GND D3 VCCO D5 NC NC
SO20/ SOG20 Top View
17 16 15 14 13 12 11
6 5 4 3 2 1 44 43 42 41 40
OE/RESET D6 CE
*See pin descriptions.
DS026_14_102005
VCCINT* TDO D1 D3 D5
*See pin descriptions.
PC20/ PCG20 Top View
10 11 12 D7
17 16 15 13 CEO 14
D6
CE
NC CLK D2 GND D0 NC VCCINT* NC VCCO VCCINT* NC
GND
*See pin descriptions.
DS026_15_20051007
NC NC TDI NC TMS GND TCK VCCO D4 CF NC
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VQ44/VQG44 Top View
NC NC TDO NC D1 GND D3 VCCO D5 NC NC
NC OE/RESET D6 CE VCCO VCCINT* GND D7 NC CEO NC
12 13 14 15 16 17 18 19 20 21 22 *See pin descriptions.
DS026_13_20051007
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XC18V00 Series In-System-Programmable Configuration PROMs
Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible PROMs. Table 2: Xilinx FPGAs and Compatible PROMs
Device
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 XCV50E XCV100E XCV200E XCV300E XCV400E
Table 2: Xilinx FPGAs and Compatible PROMs (Cont'd)
Device
XCV405E XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
Configuration Bits
1,305,376 3,006,496 4,485,408 8,214,560 11,589,920 15,868,192 19,021,344 26,098,976 34,292,768 470,048 732,576 1,726,880 2,767,520 4,089,504 5,667,488 7,501,472 10,505,120 15,673,248 21,865,376 29,081,504 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048 3,607,968 4,715,616 6,127,744 630,048 863,840 1,442,016 1,875,648 2,693,440
XC18V00 Solution
XC18V02 XC18V04 XC18V04 + XC18V512 2 of XC18V04 3 of XC18V04 4 of XC18V04 5 of XC18V04 6 of XC18V04 + XC18V512 8 of XC18V04 + XC18V512 XC18V512 XC18V01 XC18V02 XC18V04 XC18V04 XC18V04 + XC18V02 2 of XC18V04 3 of XC18V04 4 of XC18V04 5 of XC18V04 + XC18V02 7 of XC18V04 XC18V01 XC18V01 XC18V01 XC18V02 XC18V02 XC18V04 XC18V04 XC18V04 + XC18V512 XC18V04 + XC18V02 XC18V01 XC18V01 XC18V02 XC18V02 XC18V04
Configuration Bits
3,430,400 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712 197,696 336,768 559,200 781,216 1,040,096 1,335,840 630,048 863,840 1,134,496 1,442,016 1,875,648 2,693,440 3,961,632 439,264 1,047,616 1,699,136 3,223,488 5,214,784 7,673,024 11,316,864 13,271,936
XC18V00 Solution
XC18V04 XC18V04 2 of XC18V04 2 of XC18V04 2 of XC18V04 3 of XC18V04 4 of XC18V04 4 of XC18V04 XC18V512 XC18V512 XC18V01 XC18V01 XC18V01 XC18V02 XC18V01 XC18V01 XC18V02 XC18V02 XC18V02 XC18V04 XC18V04 XC18V512 XC18V01 XC18V02 XC18V04 XC18V04 + XC18V01 2 of XC18V04 3 of XC18V04 3 of XC18V04 + XC18V01
Capacity
Devices
XC18V04 XC18V02 XC18V01 XC18V512
Configuration Bits
4,194,304 2,097,152 1,048,576 524,288
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XC18V00 Series In-System-Programmable Configuration PROMs system programmable option for future enhancements and design changes.
In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx iMPACT software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-Z state or held at clamp levels during in-system programming.
Reliability and Endurance
Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit. See the UG116, Xilinx Device Reliability Report, for device quality, reliability, and process node information.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading via JTAG. Table 3 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 3: Data Security Options
Reset
Read Allowed Program/Erase Allowed Verify Allowed
OE/RESET
The ISP programming algorithm requires issuance of a reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by a third-party device programmer, providing the added flexibility of using pre-programmed devices with an in-
Set
Read Inhibited via JTAG Program/Erase Allowed Verify Inhibited
X-Ref Target - Figure 2
V CCIN
T
GND
(a)
(b)
DS026_02_06/1103
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
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XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 3
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required Boundary-Scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XC18V00 device. Table 4 lists the required and optional Boundary-Scan instructions supported in the XC18V00. Refer to the IEEE Std. 1149.1 specification for a complete description of BoundaryScan architecture and the required and optional instructions. Table 4: Boundary-Scan Instructions
Boundary-Scan Command
BYPASS SAMPLE/ PRELOAD EXTEST
IR[7:5] TDI Notes:
1.
IR[4] ISP Status
IR[3] Security
IR[2] 0
IR[1:0] 01(1) TDO
000
IR[1:0] = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence
Boundary-Scan Register
The Boundary-Scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XC18V00 has two register stages that contribute to the Boundary-Scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the high-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin.
Binary Code [7:0]
Description
Required Instructions:
11111111 Enables BYPASS 00000001 Enables Boundary-Scan SAMPLE/PRELOAD operation 00000000 Enables Boundary-Scan EXTEST operation 11111010 Enables Boundary-Scan CLAMP operation 11111100 All outputs in high-Z state simultaneously 11111110 Enables shifting out 32-bit IDCODE 11111101 Enables shifting out 32-bit USERCODE 11101110 Initiates FPGA configuration by pulsing CF pin Low once
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. See Table 5 for the XC18V00 IDCODE values. The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
Optional Instructions:
CLAMP HIGHZ IDCODE USERCODE
XC18V00 Specific Instructions:
CONFIG
where v = the die version number f = the family code (50h for XC18V00 family) a = the ISP PROM product ID (26h or 36h for the XC18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1"
as defined by IEEE Std. 1149.1.
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. The ISP Status field, IR(4), contains logic "1" if the device is currently in ISP mode; otherwise, it contains logic "0". The Security field, IR(3), contains logic "1" if the device has been programmed with the security option turned on; otherwise, it contains logic "0".
Table 5 lists the IDCODE register values for XC18V00 devices. Table 5: IDCODES Assigned to XC18V00 Devices
ISP-PROM
XC18V01 XC18V02 XC18V04 XC18V512 Notes:
1. The in the IDCODE field represents the device's revision code (in hex), and may vary.
IDCODE
05024093h 05025093h 05026093h 05023093h or or or or 5034093h 5035093h 5036093h 5033093h
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XC18V00 Series In-System-Programmable Configuration PROMs
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00 device. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh.
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single four-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XC18V00 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both BoundaryScan and ISP operations.
X-Ref Target - Figure 4
TCKMIN1,2
TCK
TMSS TMSH
TMS
TDIS TDIH
TDI
TDOV
TDO
DS026_04_032702
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4. Table 6: Test Access Port Timing Parameters
Symbol
TCKMIN1 TCKMIN2 TMSS TMSH TDIS TDIH TDOV
Parameter
TCK minimum clock period TCK minimum clock period, Bypass mode TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay
Min
100 50 10 25 10 25 -
Max
- - - - - - 25
Units
ns ns ns ns ns ns ns
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XC18V00 Series In-System-Programmable Configuration PROMs control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx iMPACT software. Serial output is the default configuration mode.
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM (see Figure 5 and Figure 6). * * The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) (in Master Serial and Master SelectMAP modes only). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCCINT glitch. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Slave Parallel/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements.
Master Serial Mode Summary
The I/O and logic functions of the FPGA's configurable logic block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed to accommodate the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration. Master Serial mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dualfunction DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor.
* *
*
*
Initiating FPGA Configuration
The XC18V00 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF Low once for 300-500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The iMPACT software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting. The 20-pin packages do not have a dedicated CF pin. For 20-pin packages, the CF D4 setting can be used to route the CF pin function to pin 7 only if the parallel output mode is not used.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (Figure 7 and Figure 8). Multiple XC18V00 devices can be cascaded by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all XC18V00 devices in the chain are interconnected. After the last data from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-Z state. The second PROM recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low or CE goes High.
Selecting Configuration Modes
The XC18V00 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XC18V00 device. This
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XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 5
VCCO(2)
4.7 k
4.7 k
(1)
VCCO VCCINT
VCCINT VCCO(2)
D0
DIN
MODE PINS(1) DIN CCLK
XC18V00 PROM
CLK CE CEO OE/RESET TDI TMS TCK TDO TDO GND TDI TDI TMS TCK CF
Xilinx FPGA Master Serial
CCLK DONE DOUT INIT_B (INIT) PROG_B (PROGRAM)
DONE INIT_B (INIT) PROG_B (PROGRAM)
...OPTIONAL Slave FPGAs with identical configurations
DOUT CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
...OPTIONAL Daisy-chained Slave FPGAs with different configurations
TMS TCK TDO
GND
Notes: 1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide. 2 For compatible voltages, refer to the appropriate data sheet.
ds026_18_20051007
Figure 5: Master Serial Mode
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XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 6
External Oscillator(3) VCCO VCCINT
VCCO(2)
4.7 k
4.7 k
(1)
8
VCCINT VCCO(2)
D[0:7]
D[0:7]
MODE PINS
(1)
RDWR_B CS_B
XC18V00 PROM
CLK TDI TMS TCK TDO CE CEO OE/RESET CF TDO GND
Xilinx FPGA SelectMAP or Slave-Parallel
CCLK DONE INIT_B (INIT) PROG_B (PROGRAM) TDI TMS TCK GND TDO D[0:7] CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
...OPTIONAL Slave FPGAs with identical configurations
Notes: 1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide. 2 For compatible voltages, refer to the appropriate data sheet. 3 External oscillator required for Virtex/Virtex-E SelectMAP, for Virtex-II/Virtex-II Pro Slave SelectMAP, and for Spartan-II/Spartan-IIE Slave-Parallel modes.
DS026_19_111207
Figure 6: Master/Slave SelectMAP Mode or Slave Parallel Mode
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XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 7
VCCO VCCINT
VCCO VCCINT
VCCO
(2)
4.7 k
4.7 k
(1)
VCCINT VCCO
(2)
D0
VCCINT VCCO
(2)
D0
DIN
MODE PINS
(1)
MODE PINS(1) DIN
DOUT
XC18V00 PROM Cascaded PROM (PROM 1)
TDI TMS TCK TDO CLK CE CEO OE/RESET TDI TMS TCK TDO CF
XC18V00 PROM First PROM (PROM 0)
CLK CE CEO OE/RESET CF TDI TMS TCK TDO TDI
Xilinx FPGA Master Serial
CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
Xilinx FPGA Slave Serial
CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
TDO
TDI TMS TCK TDO
GND
GND
TMS TCK
GND
GND
Notes: 1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide. 2 For compatible voltages, refer to the appropriate data sheet.
ds026_16_20051007
Figure 7: Configuring Multiple Devices in Master/Slave Serial Mode
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XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 8
VCCO VCCINT
External (4) Oscillator
VCCO VCCINT
VCCO
(2)
4.7 k
4.7 k
(1)
8
8
VCCINT VCCO(2)
D[0:7](3)
VCCINT VCCO(2)
D[0:7](3)
D[0:7](3)
MODE PINS
(1)
D[0:7]
(3)
MODE PINS
(1)
RDWR_B
(3) (3)
RDWR_B CS_B
(3) (3)
XC18V00
PROM Cascaded PROM (PROM 1)
XC18V00
PROM First PROM (PROM 0)
CS_B
Xilinx FPGA Master Serial/SelectMAP
CLK CE CEO CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
Xilinx FPGA Slave Serial/SelectMAP
CCLK DONE INIT_B (INIT) PROG_B (PROGRAM)
CLK CE CEO
OE/RESET TDI TMS TCK TDO GND TDI TMS TCK TDO TDI TMS TCK GND CF
OE/RESET CF
TDO
TDI TMS TCK
TDO
TDI TMS TCK TDO
GND
GND
Notes: 1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide. 2 For compatible voltages, refer to the appropriate data sheet. 3 Serial modes do not require the D[1:7], RDWR_B, or CS_B pins to be connected. 4 External oscillator required if CLK is not supplied by an FPGA in Master mode. Refer to the appropriate FPGA data sheet.
DS026_17_111207
Figure 8: Configuring Multiple Devices with Identical Patterns in Master/Slave Serial, Master/Slave SelectMAP, or Master/Slave Parallel Mode
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XC18V00 Series In-System-Programmable Configuration PROMs
Reset and Power-On Reset Activation
At power up, the device requires the VCCINT power supply to rise monotonically to the nominal operating voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on reset properly. During the power-up sequence, OE/RESET is held Low by the PROM. Once the required supplies have reached their respective POR (Power On Reset) thresholds, the OE/RESET release is delayed (TOER minimum) to allow more margin for the power supplies to stabilize before initiating configuration. The OE/RESET pin is connected to an external pull-up resistor and also to the target FPGA's INIT_B pin. For systems utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the OE/RESET pin Low. When OE/RESET is released, the FPGA's INIT_B pin is pulled High, allowing the FPGA's configuration sequence to begin. If the power drops below the power-down threshold (VCCPD), the PROM resets and OE/RESET is again held Low until the after the POR threshold is reached. OE/RESET polarity is not programmable. These power-up requirements are shown graphically in Figure 9. For a fully powered Platform Flash PROM, a reset occurs whenever OE/RESET is asserted (Low) or CE is deasserted (High). The address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-Z state.
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The address is reset. The output remains in a high-Z state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be in a high-Z state or High. See Table 7. When using the FPGA DONE signal to drive the PROM CE pin High to reduce standby power after configuration, an external pull-up resistor should be used. Typically a 330 pull-up resistor is used, but refer to the appropriate FPGA data sheet for the recommended DONE pin pull-up value. If the DONE circuit is connected to an LED to indicate FPGA configuration is complete, and also connected to the PROM CE pin to enable low-power standby mode, then an external buffer should be used to drive the LED circuit to ensure valid transitions on the PROMs CE pin. If low-power standby mode is not required for the PROM, then the CE pin should be connected to ground.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCCINT power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCCINT), and the output power supply (VCCO) can have power applied in any order. This makes the PROM devices immune to power supply sequencing issues.
X-Ref Target - Figure 9
VCCINT
Recommended Operating Range Delay or Restart Configuration
200 s ramp
50 ms ramp
VCCPOR VCCPD
A slow-ramping VCCINT supply may still be below the minimum operating voltage when OE/RESET is released. In this case, the configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.
TIME (ms) TRST
ds026_20_032504
TOER
TOER
Figure 9: VCCINT Power-Up Requirements
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XC18V00 Series In-System-Programmable Configuration PROMs
Customer Control Bits
The XC18V00 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using "Skip User Array" in Xilinx iMPACT software. The iMPACT software can set these bits to enable the optional JTAG read security, parallel configuration mode, or CF D4 pin function. See Table 7. Table 7: Truth Table for PROM Control Inputs
Control Inputs OE/RESET
High Low High Low Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
CE
Low Low High High
Internal Address
If address < TC(1): increment If address > TC(1): don't change Held reset Held reset Held reset
Outputs DATA
Active high-Z High-Z High-Z High-Z
CEO
High Low High High High
ICC
Active reduced Active Standby Standby
Absolute Maximum Ratings(1,2)
Symbol
VCCINT/VCCO VIN VTS TSTG TJ Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Description
Supply voltage relative to GND Input voltage with respect to GND Voltage applied to high-Z output Storage temperature (ambient) Junction temperature
Value
-0.5 to +4.0 -0.5 to +5.5 -0.5 to +5.5 -65 to +150 +125
Units
V V V C C
2.
Supply Voltage Requirements for Power-On Reset and Power-Down
Symbol
TVCC VCCPOR TOER TRST VCCPD Notes:
1. 2. 3. VCCINT and VCCO supplies can be applied in any order. At power up, the device requires the VCCINT power supply to rise monotonically to the nominal operating voltage within the specified TVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 9, page 14. If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions. Typical POR is value is 2.0V.
Description
VCCINT rise time from 0V to nominal OE/RESET release delay following voltage (2)
Min
0.2 1 0 10 -
Max
50 - 1 - 1
Units
ms V ms ms V
POR threshold for the VCCINT supply POR (3) Time required to trigger a device reset when the VCCINT supply drops below the maximum VCCPD threshold Power-down threshold for VCCINT supply
4.
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XC18V00 Series In-System-Programmable Configuration PROMs
Recommended Operating Conditions
Symbol
VCCINT VCCO VIL VIH VO TVCC TA Notes:
1. 2. At power up, the device requires the VCCINT power supply to rise monotonically from 0V to nominal voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 9, page 14. Covers the industrial temperature range.
Parameter
Internal voltage supply Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Low-level input voltage High-level input voltage Output voltage VCCINT rise time from 0V to nominal Operating ambient temperature(2) voltage(1)
Min
3.0 3.0 2.3 0 2.0 0 1 -40
Max
3.6 3.6 2.7 0.8 5.5 VCCO 50 85
Units
V V V V V V ms C
Quality and Reliability Characteristics
Symbol
TDR NPE VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge (ESD)
Description
Min
20 20,000 2,000
Max
- - -
Units
Years Cycles Volts
DC Characteristics Over Operating Conditions
Symbol
VOH VOL ICC ICCS IILJ IIL IIH CIN
Parameter
High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs Low-level output voltage for 3.3V outputs Low-level output voltage for 2.5V outputs Supply current, active mode Supply current, standby mode JTAG pins TMS, TDI, and TDO pull-up current (1) Input leakage current Input and output high-Z leakage current Input capacitance Output capacitance
Test Conditions
IOH = -4 mA IOH = -500 A IOL = 8 mA IOL = 500 A 25 MHz VCCINT = MAX VIN = GND VCCINT = Max VIN = GND or VCCINT VCCINT = Max VIN = GND or VCCINT VIN = GND f = 1.0 MHz VOUT = GND f = 1.0 MHz
Min
2.4 90% VCCO - - - - - -10 -10 - -
Max
- - 0.4 0.4 25 10 100 10 10 8
Units
V V V V mA mA A A A pF
COUT
Notes:
1.
14
pF
Internal pull-up resistors guarantee valid logic levels at unconnected input pins. These pull-up resistors do not guarantee valid logic levels when input pins are connected to other circuits.
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V04 and XC18V02
CE
TSCE THCE
OE/RESET
TLC THC TCYC THOE
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS026_06_012000
Symbol
TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE Notes:
1. 2. 3. 4. 5. 6.
Description
OE/RESET to data delay CE to data delay CLK to data delay Data hold from CE, OE/RESET, or CLK CE or OE/RESET to data float delay(2) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (guarantees proper counting)(3) CE High time (guarantees counters are reset) OE/RESET hold time (guarantees counters are reset)
Min
- - - 0 - 50 10 10 25 250 250
Max
10 20 20 25 - - - - - -
Units
ns ns ns ns ns ns ns ns ns
ns
ns
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. If THCE High < 2 s, TCE = 2 s. If THOE Low < 2 s, TOE = 2 s.
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V01 and XC18V512
CE
TSCE THCE
OE/RESET
TLC THC TCYC THOE
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS026_06_012000
Symbol
TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE Notes:
1. 2. 3. 4. 5. 6.
Description
OE/RESET to data delay CE to data delay CLK to data delay Data hold from CE, OE/RESET, or CLK CE or OE/RESET to data float delay(2) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (guarantees proper counting)(3) CE High time (guarantees counters are reset) OE/RESET hold time (guarantees counters are reset)
Min
- - - 0 - 30 10 10 20 250 250
Max
10 15 15 - 25 - - - - - -
Units
ns ns ns ns ns ns ns ns ns
ns
ns
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. If THCE High < 2 s, TCE = 2 s. If THOE Low < 2 s, TOE = 2 s.
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02
OE/RESET
CE
CLK
TCDF TOCE First Bit TOOE
DATA
Last Bit TOCK
CEO
DS026_07_020300
Symbol
TCDF TOCK TOCE TOOE Notes:
1. 2. 3. 4. 5.
Description
CLK to data float CLK to CEO CE to CEO delay(2,3) delay(3) delay(3)
Min
- - - -
Max
25 20 20 20
Units
ns ns ns ns
delay(3)
OE/RESET to CEO
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. For cascade mode: TCYC min = TOCK + TCE + FPGA DIN-to-CCLK setup time
TCAC min = TOCK + TCE
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V01 and XC18V512
OE/RESET
CE
CLK
TCDF TOCE First Bit TOOE
DATA
Last Bit TOCK
CEO
DS026_07_020300
Symbol
TCDF TOCK TOCE TOOE Notes:
1. 2. 3. 4. 5.
Description
CLK to data float CLK to CEO CE to CEO delay(2,3) delay(3) delay(3)
Min
- - - -
Max
25 20 20 20
Units
ns ns ns ns
delay(3)
OE/RESET to CEO
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. For cascade mode: TCYC min = TOCK + TCE + FPGA DIN-to-CCLK setup time
TCAC min = TOCK + TCE
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XC18V00 Series In-System-Programmable Configuration PROMs
Ordering Information
XC18V04 VQ44 C
Device Number XC18V04 XC18V02 XC18V01 XC18V512 Package Type VQ44 = 44-pin Plastic Quad Flat Package VQG44 = 44-pin Plastic Quad Flat Package, Pb-free PC44 = 44-pin Plastic Chip Carrier(1) PCG44 = 44-pin Plastic Chip Carrier, Pb-free(1) SO20 = 20-pin Small-Outline Package(2) SOG20 = 20-pin Small-Outline Package, Pb-free(2) PC20 = 20-pin Plastic Leaded Chip Carrier(2) PCG20 = 20-pin Plastic Leaded Chip Carrier, Pb-free(2)
Notes:
1. 2. XC18V04 and XC18V02 only. XC18V01 and XC18V512 only.
Operating Range C = Industrial (TA = -40 C to +85 C)
Valid Ordering Combinations
XC18V04VQ44C XC18V04PC44C XC18V04VQG44C XC18V04PCG44C XC18V02VQ44C XC18V02PC44C XC18V02VQG44C XC18V02PCG44C XC18V01VQ44C XC18V01PC20C XC18V01SO20C XC18V01VQG44C XC18V01PCG20C XC18V01SOG20C XC18V512VQ44C XC18V512PC20C XC18V512SO20C XC18V512VQG44C XC18V512PCG20C XC18V512SOG20C
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XC18V00 Series In-System-Programmable Configuration PROMs
Marking Information
44-pin Package Device Number XC18V04 XC18V02 XC18V01 XC18V512 Package Type
XC18V04 VQ44
Operating Range [no mark] = Industrial (TA = -40 C to +85 C)
VQ44 = 44-pin Plastic Quad Flat Package VQG44 = 44-pin Plastic Quad Flat Package, Pb-Free PC44 = 44-pin Plastic Leaded Chip Carrier(1) PCG44 = 44-pin Plastic Leaded Chip Carrier, Pb-Free(1)
Notes:
1. XC18V02 and XC18V04 only.
20-pin Package(1) Due to the small size of the serial PROM packages, the complete ordering part number cannot be marked on the package. The package code is simplified. Device marking is as follows:
XC18V01 S
Device Number 18V01 18V512 Package Type Operating Range [no mark] = Industrial (TA = -40 C to +85 C)
S = 20-pin Small-Outline Package(2) SG = 20-pin Small-Outline Package, Pb-free(2) J = 20-pin Plastic Leaded Chip Carrier(2) JG = 20-pin Plastic Leaded Chip Carrier, Pb-free(2)
Notes:
1. 2. Refer to XC18V00 PROM product change notices (PCNs) for legacy part markings. XC18V01 and XC18V512 only.
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XC18V00 Series In-System-Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document.
Date
02/09/99 08/23/99 09/01/99 09/16/99 01/20/00 02/18/00 04/04/00 06/29/00 11/13/00
Version
1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4
Revision
First publication of this early access specification Edited text, changed marking, added CF and parallel load Corrected JTAG order, Security and Endurance data. Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF description, 256 Kbit and 128 Kbit devices. Added Q44 Package, changed XC18xx to XC18Vxx Updated JTAG configuration, AC and DC characteristics Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to FPGA table. Removed XC18V128 and updated format. Added AC characteristics for XC18V01, XC18V512, and XC18V256 densities. Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: TSCE units to ns, THCE CE High time units to s. Removed Standby mode statement: "The lower power standby modes available on some XC18V00 devices are set by the user in the programming software". Changed 10,000 cycles endurance to 20,000 cycles. Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP PROM product ID from 06h to 26h. Updated Figure 8, Virtex SelectMAP mode; added XC2V products to Compatible PROM table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years; Updated Figure 8: removed Virtex-E in Note 2, fixed SelectMAP mode connections. Under "AC Characteristics Over Operating Conditions for XC18V04 and XC18V02", changed TSCE from 25 ms to 25 ns. "AC Characteristics Over Operating Conditions for XC18V01 and XC18V512". Changed Min values for TSCE from 20 ms to 20 ns and for THCE from 2 ms to 2 s. Changed the Boundary-Scan order for the CEO pin in Table 1, updated the configuration bits values in the table under "Xilinx FPGAs and Compatible PROMs", and added information to the "Recommended Operating Conditions" table. Updated for Spartan-IIE FPGA family. Changed Figure 5(c). Updated Table 2 and Figure 8 for the Virtex-II Pro family of devices. Updated Xilinx software and modified Figure 8 and Figure 5. Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 9 and Figure 9. Made additions and changes to Table 2. Changed last bullet under Connecting Configuration PROMs, page 9. Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and the deletion of Figure 9. Made minor change on Figure 5 (b) and changed orientation of SO20 diagram on page 5. Added XC2S400E and XC2S600E to Table 2. Changes to "Description", "External Programming", and Table 2.
01/15/01 04/04/01 04/30/01
2.5 2.6 2.7
06/11/01 09/28/01
2.8 2.9
11/12/01 12/06/01 02/27/02 03/15/02 03/27/02 06/14/02 07/24/02 09/06/02 10/31/02 11/18/02 04/17/03
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10
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XC18V00 Series In-System-Programmable Configuration PROMs
06/11/03
4.0
Major revision. * Added alternate IDCODES to Table 5. * Discontinued XC18V256 density. * Eliminated industrial ordering combinations. * Extended commercial temperature range. * Added MultiPRO Desktop Tool support. * Changed THOE and THCE to 250 ns in the tables on page 17 and page 18. * Made change in capacitance values "DC Characteristics Over Operating Conditions". * Added Note (3) to Table 1. * Other minor edits. Added specification (4.7 k) for recommended pull-up resistor on OE/RESET pin to section Reset and Power-On Reset Activation, page 14. Added paragraph to section Standby Mode, page 14, concerning use of a pull-up resistor and/or buffer on the DONE pin. Major revision. * Figure 2: Revised configuration bitstream lengths for most Virtex-II FPGAs. * Replaced previous schematics in Figures 5, 6, 7(a), 7(b), and 7(c) with new Figure 5, Figure 6, Figure 7, and Figure 8. * Replaced previous Figure 8 with new Figure 9. * Replaced previous power-on text section with new Reset and Power-On Reset Activation, page 14. * Added specification table Supply Voltage Requirements for Power-On Reset and Power-Down, page 15. * Added Footnote (5) to: Specification table AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02, page 19. Specification table AC Characteristics Over Operating Conditions When Cascading for XC18V01 and XC18V512, page 20. * Numerous copyedits and wording changes/clarifications throughout. Table 2: Removed reference to XC2VP125 FPGA. * Added Pb-free packages to Features, page 1, Pinout Diagrams, page 4,"Ordering Information", Valid Ordering Combinations, page 21and Marking Information, page 22. * Removed maximum soldering temperature (TSOL) from Absolute Maximum Ratings(1,2), page 15. Refer to Xilinx Device Package User Guide for package soldering guidelines. * Added information to Table 5 regarding variable JTAG IDCODE revision field. * Updated document template. * Updated URLs. * Tied RDWR_B and CS_B to GND to ensure valid logic-level Low in FPGA SelectMAP mode in Figure 6, page 11 and Figure 8, page 13. * Updated "Marking Information," page 22 for 20-pin packaging.
12/15/03
4.1
04/05/04
5.0
07/20/04 03/06/06
5.0.1 5.1
01/11/08
5.2
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
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